home / Instructor resources / Additional problems

Additional Problems

The textbook contains many homework problems.  Here is a list of additional homework problems or exercises that can be used in conjunction with teaching.  Problems are categorized into two areas: concepts, design.  We also rank the level of questions. Questions are categorized into * Basics, ** Intermediate, and *** Advanced.  

C001: (***) Compare three surface micromachined structural layers: LPCVD polycrystalline silicon, epitaxial silicon, and silicon germanium.
C002: (**) Investigate options for realizing silicon suspension structures with 10 micrometer thickness
C003: (***) Investigate the TSV (through silicon via technology) and conduct a literature survey
C004: (**) Conduct a literature review of AlGe eutectic bonding process.  Compare this with other eutectic bonding techniques. 
C005: (**) Review the patents of Knowles (U.S. Patents 6,781,231 and 7,242,089), along with the saga of patent battle between leading companies, and determine whether you agree with the ITC judge or not on his November/December 2010 decisions about patent infringement.
C006: (**) Examine the difference of technology for display from three of the following companies: PlasticLogic, PixieQi, Samsung LCD, Qualcomm Mirasol, Pixtronics
C007: (*) Investigate a company out of the list of MEMS companies and describe its technology, fabrication, and industrial selling point.

D001: (*) Scaling laws for digital light processor
D002: (*) Evaluate the process compatibility of a surface micromachining processing using LPCVD oxide as sacrificial layer and LPCVD polysilicon as structural layer.
D003: (*) Critic/analyze process (surface micromachining, no design issue involved)
D004: Critic/analyze process for Texas Instruments DLP (surface micromachining, no design issue involved)
D005: Critic process (surface micromachining, no design issue involved)
D006: Critic process (surface or bulk micromachining, no design issue involved) 
D007: Critic process (surface or bulk micromachining, no design issue involved) 
D008: Critic process (surface and/or bulk micromachining, no design issue involved) 
D009: Synthesize process (surface micromachining, no design variable)
D010: Synthesize process (surface micromachining, no design variable)
D010: Critic process (surface micromachining, with design issue involved)
D011: Critic process (surface micromachining, with design issue involved)
D012: Critic process (surface and/or bulk micromachining, with design issue involved)
D013: Critic process (surface and/or bulk micromachining, with design issue involved)
D014: Synthesize process (surface micromachining, with design issue involved)
D015: Synthesize process (surface micromachining, with design issue involved)
D016: Synthesize process (surface micromachining, with design issue involved)
D017: Synthesize process (surface and/or bulk micromachining, with design issue involved)
D018: Synthesize process (surface and/or bulk micromachining, with design issue involved)
D019: Synthesize process (surface and/or bulk micromachining, with design issue involved)
D020: Synthesize process (surface and/or bulk micromachining, with design issue involved)
D021: Bulk etching process (which is impossible)
D022: Bulk etching + Materials for bridge
D023: Bulk etching + materials + conductors
D024: Surface vs. bulk for making a bridge.


D002: Evaluate the process compatibility of an established surface micromachining technology

The use of LPCVD polysilicon as structural layer and LPCVD oxide as sacrificial layer is a well established technique. It uses materials that the circuit industry already uses. It is implemented for Analog Devices accelerometer, a successful commercial product. Evaluate the following aspect of the process compatibility:
1. What is the material for etching sacrificial layer? Does the material used for etching the sacrificial layer attacks the structural layer?
2. What is a good process for etching and defining the structural layer? does this process attacks the underlying sacrificial layer? what is the selectivity?
3. Does the deposition of the structural layer harm the underlying sacrificial layer?
4. What is the commonly encountered intrinsic stress level of the LPCVD polysilicon? what are process techniques to reduce the stress?

Hint: you may refer to papers by Kirt Williams or the simplified MEMS material tables Table of commonly encountered MEMS materials Table of commonly used processing methods Table of reaction between the common materials and processes

D003: Critic/analyze two surface micromachining processes.

A surface micromaching process uses LPCVD silicon oxide as a sacrificial layer and LPCVD polysilicon as a structural layer. The desired spacing under the polysilicon is 2 microns. The desired thickness of the polysilicon layer is 3 microns. The polysilicon layer is patterned using plasma etching, using hardbaked photoresist as mask.

(a) Consider two options, one uses SF6 plasma to etch the silicon, and one uses CF4 plasma to etch the silicon. What is the required etching time in each case? what is the respective minimal thickness of photoresist required for each process? In this case, discuss which etching method you would use.


(b) Assume there is 10% variation of etch speed across a wafer. Suppose this variation is due to inevitable location-based etch rate variation across a wafer. Again, we compare SF6 and CF4 cases. While device on one side is perfectly etched through, one device on the other side may be over etched. To ensure that all devices on a wafer is successful (i.e., the polysilicon is etched through everywhere), what is the time you would apply to the plasma etching? what is the minimal thickness of photoresist required under the worst case scenario? what is the maximum over etching depth in the sacrificial layer?

(Consult Table of commonly encountered MEMS materials Table of commonly used processing methods Table of reaction between the common materials and processes.)

D004: Critic/analyze process for Texas Instruments DLP

The Digital Light Processor (DLP) from Texas Instruments is a true engineering wonder developed by visionaries.  Draw the process flow for building the MEMS mirror device, and include at least 8 steps.  From literature, find out or speculate about the materials for the TI process, considering both thickness achievable, stress and planarity, and etching selectivity.


Copyrighted material, 2011.  You may use it freely for educational purposes.